Memory Modules

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ROM (BIOS)
Non-volitale memory
ROM and RAM are NOT opposites.
Main ROM BIOS is contained in a ROM chip on the motherboard.
There also found in adapter cards and removable storage (thumb drives).
Today, we use a type of ROM called EEPROM or Flash ROM.

DRAM (Dynamic)
Requires that data be refreshed (essentially rewritten) every millisecond
Industry-standard refresh time is 15ms
Refresh occurs when the memory controller accesses all the rows of data in the memory chip.
DRAM uses only 1 transistor and 1 capacitor pair per bit
Available with one billion or more transistors
Tiny capacitors must retain their charge, or memory will be lost
The DRAM chip mostly is used for the main memory
Very dense (pack a lot of bits into a very small chip)
Inexpensive
Unfortunately its very slow

SRAM (Static)
Consists of levels of Cache
L1 (internal cache) –always built into the processor die.
L2 (external cache) –originally installed on the motherboard but now on the processor die running at full core speed.
L3 –is present in high-end workstations and server processors (Pentium 4 Extreme Edition).
Available in access times of 2ns or less. Capable of keeping pace with modern processors.
Calls for 6 transistors for each bit of storage (no capacitors)
30 times larger and 30 times more expensive than DRAM.
Doesn’t need the periodic refresh rates like DRAM.
Cache effectiveness is expressed as a hit ratio
Pipeline burst mode –reduced overall cache latency (wait states) by allowing single-cycle accesses for multiple transfers after the first one.
Cache Controller –dictates the cache’s performance and capabilities
Cache Controller is located on the CPU die along with & L2 cache, or in the north bridge when L2 cache was originally on the motherboard.
Its important NOT to install more memory than the cache controller can support

Memory Flow Chart
MEMORY MODULES
History
Over the years two main changes have occurred in computer memory –it has gradually become faster and wider. The 8088 and 8086 CPU’s, with 20 address lines (2^20), can use as much as 1MB (1,024KB) of RAM. The Itanium processor, with 44-bit addressing (2^44), allows for up to 16TB of Physical RAM. Originally, individual chips that were used as memory were often referred to as DIP chips because of their design.

DIP (Dual Inline Package)
Took hours populating boards
Time-consuming and labor-intensive
Chip creep -they crept out of their sockets over time as the system went through thermal cycles

SIPP’s (Single Inline Pin Package)
Little tiny wires for individual sockets
The wires would bend
Their omitted

SIMM’s (Single Inline Memory Module)
Only has one row of signal pins
Both sides are still the same connectors

DIMM’s (Dual Inline Memory Module)
Seperate row of signal pins on each side
More than 200 signal pins

RIMM’s (Rambus Inline Memory Module)
Have different signal pins on each side
Mostly obsolete

You can almost always substitute faster speeds of memory modules. Although it doesn’t mean your system will perform faster.
If you mix RAM, your system will run at the speed of the slowest RAM.

ANOTCH KEY DEFINITION
DIMM Notches
DIMM Nothes
Parity (Non-maskable Interrupt)
For every Byte of data you’ll have a 9th bit for detecting if you have corrupted data.
It doesn’t improve the capacity of the RAM
Odd parity –all 9 bits are odd
Even parity –all 9 bits are evenly spread

ECC(Error Correction Code)
Detects and fixes bad data

Logical Memory Map
BANKING
Memory chips are organized in banks on motherboards and memory cards. The banks usually correspond to the data bus of the systems microprocessor.

There was a time that memory was worth more than its weight in gold; since then, under 13 cents per megabyte.

Memory Modules used gold plated contacts and tin plated. If you mix different contacts your likely to experience memory failure form six months to a year after initial installation because of a type of corrosion known as fretting will take place.

Most Modern PC’s are designed to use unbuffered modules.

Registered Modules are required when using extremely large amounts of RAM.

If the motherboard uses presence detect signals, a POST procedure can determine the size and speed of the installed SIMMs and adjust control and addressing signals automatically. This enables autodetection of the memory size and speed.

DIMM uses SPD and SIMM uses Presence detect