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Microprocessor Die


Data (I/O) Bus – (external data bus); A bundle of wires (or pins) used to send and receive data.
    • Processor data bus is also called the front side bus (FSB), processor side bus (PSB), or just CPU bus
    • The speed and width of a processor external data bus is perhaps the most important feature.
    • The width of the data bus also defines the size of a bank of memory.
    • The size of this bus indicates the chips information-moving capability.
    • A wider data bus is like having a highway with more lanes, which enables greater throughput.


Address Bus –the set of wires that carries the addressing information used to describe the memory location to which the data is being sent, or from which the data is being retrieved.
    • The more wires (digits) used in calculating these addresses, the greater the total number of address locations
    • The size (or width) of the address bus indicates the maximum amount of RAM a chip can address.
    • The size of this bus determines how much memory the chip can handle.
    • The address bus relates to the house number or street address.
    • The size of the address bus is equivalent to the number of digits in the house address number.
    • Calculation for determining physical addressing capabilities = (2^#of bits).


Internal Registers – (internal data bus);
    • The size of the internal register indicates how much information the processor can operate on at one time and how it moves data around internally within the chip.
    • Internal registers are often larger than the data bus, which means the chip requires two cycles to fill a register before the register can be operated on
    • a register is a holding cell within the processor
    • the register sizes determines the size of data on which the processor can operate and the type of software or commands and instructions a system can run.


The various operating environments and effect the instructions and capabilities of the chip.
    • Real Mode
      • Software must use only 16-bit instructions and live within the 20-bit (1MB) memory architecture it supports.
      • Single tasking
    • IA-32 mode>
      • Could run a 32-bit instruction set
      • Was referred to as protected mode
    • IA-32 Virtual Real Mode
      • A virtual real mode 16-bit environment that runs inside 32-bit protected mode
    • IA-32e 64-bit Extension mode (AMD64, x86-64, EM64T)
      • Enables you to run in real mode and virtual
      • 64-bit mode
      • Compatibility mode -64-bit and 32-bit environment
Different instruction execution times (in cycles) make comparing systems based purely on clock speed or number of cycles per second difficult. CPUs with different architectures do things differently and can be relatively faster at certain things and slower at others. To fairly compare various CPUs these benchmarks are used:


iCOMP (Intel Comparative Microprocessor Performance)
  • An Intel based index that can be run against processors to produce a relative gauge of performance.
  • A commercially available application-based benchmark that reflects the normal usage of business users employing modern internet connection and Microsoft Office applications
Raw MHz (or GHz) is not always a good way to compare chips. Even though the processor still notes the speed of the chip, its marked primarily by model number. This is necessary because the relative difference between each model number is based not just on the CPU’s speed, but also on architectural and other differences that affect overall performance.
The processor speed can be set higher than the rating of the chip
  • You can get away with a certain amount of overclocking because CPU’s were originally built with safety margins into their ratings.
  • An 800MHz processor could run at 900MHz or more with the exception of down-rating (margin of reliability)
  • Newer Intel boards have a “burn-in” feature that allows you to increase the default processor bus speed by up to 4%.
  • FC-PGA  format, which plugs into Socket A, have special solder bridges on the top face of the chip that can be modified to change or remove the lock from the internal multiplier on the chip, further increasing the speed of the chip without changing the motherboard bus speed, thus affecting other busses or cards.
  • By either increasing or decreasing voltages slightly from the standard, a higher speed of overclock can be achieved with the system remaining stable.
A high-speed memory buffer that temporarily stores data the processor needs, allowing the processor to retrieve that data faster than if it came from main memory.
  • L1
  • L2
  • L3
Cache speed is always more important than size.
Cache stores copies of data from various main memory addresses. If we need data from those addresses, it can be read from the cache rather than from the main memory.
  • Tag RAM –additional memory in the cache that holds an index of the addresses that are copied into the cache.<
  • Write-through –when the processor writes information out to the cache, that information is automatically written through to main memory (RAM) as well.
  • Write-back –both reads and writes are cached, further improving performance.
  • Non-blocking –enable program execution to proceed concurrently with cache misses as long as certain dependency constraints are observed.
  • Bus snooping –watching the memory bus when alternative processors, known as bus masters, are in control of the system.
If the requested main memory address is found in the Tag RAM its a.
If the requested address is not found in the address Tag entries its a.
SMM (system management mode)
  • Enables the processor to conserve energy use and lengthen battery life.
Superscalar Execution
  • the ability to run more than one process in any one clock cycle
  • RISC (reduced instruction set computer)

    • Simpler instruction in executable code
  • CISC (complex instruction set computer)

    • Broad-complicated instruction in executable code
MMX Technology (multi-media extensions, or matrix math extensions)
  • An add-on that improved video compression/decompression, image manipulation, encryption, and I/O processing.
  • It extended the processor instruction set to 57 new commands, as well as new instruction capability called SIMD.
SSE (streaming single instruction, multiple data extensions)
  • Next generation of MMX
  • Added 144 additional SIMD instructions
  • An AMD feature!
  • Basically the same as SSE
Dynamic Execution
  • Branch Prediction
    • Predicts the flow of the program through several branches.
    • Enables the processor to keep the instruction pipeline full while running at high rate of speed.
  • Dataflow Analysis

    • Schedules instructions to be executed when ready; independent of their order in the original program.
    • Studies the flow of data through the processor to detect any opportunities for out-of-order instruction execution.
  • Speculative Execution

    • Increases the rate of execution by looking ahead of the program counter and executing instructions that are likely to be necessary.
    • Capability to execute instructions in advance of the actual program counter.
Dual Independent Bus (DIB) Architecture
  • DIB was created to improve processor bus bandwidth and performance.
  • Having two (dual) independent data I/O buses enables the processor to access data from either of its buses simultaneously and in parallel, rather than singular sequential manner (as is a single-bus system).
  • The main (front side bus) processor is the interface between the processor and the motherboard or chipset.
  • The second (back-side bus) bus in a processor with DIB is used for L2 cache, enabling it to run at much greater speeds than if it were to share the main processor bus.
Hyper-Threading Technology (HT)
  • Converts a single processor into two virtual processors enabling it to handle two independent sets of instructions at the same time.
Dual-core Technology
  • designed to simulate two processors in a single physical unit.


PGA chips take its name from the fact that the chip has a grid-like array of pins on the bottom of the package.They were often inserted into sockets which are often of a ZIF design.
SPGA chips used staggered pins on the underside of the chip rather than in standard rows and columns. This was done to move pins closer together and decrease overall size of the chip when a large number of pins is required.
FC-PGA were used for most modern processors. There were problems with the installation of these packages. When you would go to intall your heatsink if you pressed down on one side of the heatsink excessively during the installation you would risk cracking the silcon die (the heatsink sat on-top of the die like a pedestal) and destroying the chip.


SECC or SEPP consisted of the CPU and optional separate L2 cache chips mounted on a circuit board that looked similar to an over-sized memory module and that plugged into a slot. In some cases, the boards were covered with a plastic cartridge cover. A cost-effective method for integrating the L2 cache into the processor.
SEP was a less expensive version of the SECC just without the fancy plastic cover.
Socket 1
Socket 2
Socket 4
Socket 5
Socket 6
Socket 7
Super Socket 7
Socket 8
Socket 370 (PGA-370)
Socket 423
Socket 478
Socket A (Socket 462)
Socket 603
Socket 754
Socket 939
Socket 940
Socket T
Socket M2