Data (I/O) Bus – (external data bus); A bundle of wires (or pins) used to send and receive data.
Address Bus –the set of wires that carries the addressing information used to describe the memory location to which the data is being sent, or from which the data is being retrieved.
Internal Registers – (internal data bus);
The various operating environments and effect the instructions and capabilities of the chip.
PROCESSOR SPEED RATINGS
Different instruction execution times (in cycles) make comparing systems based purely on clock speed or number of cycles per second difficult. CPUs with different architectures do things differently and can be relatively faster at certain things and slower at others. To fairly compare various CPUs these benchmarks are used:
iCOMP (Intel Comparative Microprocessor Performance)
Raw MHz (or GHz) is not always a good way to compare chips. Even though the processor still notes the speed of the chip, its marked primarily by model number. This is necessary because the relative difference between each model number is based not just on the CPU’s speed, but also on architectural and other differences that affect overall performance.
The processor speed can be set higher than the rating of the chip
A high-speed memory buffer that temporarily stores data the processor needs, allowing the processor to retrieve that data faster than if it came from main memory.
Cache speed is always more important than size.
Cache stores copies of data from various main memory addresses. If we need data from those addresses, it can be read from the cache rather than from the main memory.
If the requested main memory address is found in the Tag RAM its a.
If the requested address is not found in the address Tag entries its a.
SMM (system management mode)
MMX Technology (multi-media extensions, or matrix math extensions)
SSE (streaming single instruction, multiple data extensions)
Dual Independent Bus (DIB) Architecture
Hyper-Threading Technology (HT)
PGA chips take its name from the fact that the chip has a grid-like array of pins on the bottom of the package.They were often inserted into sockets which are often of a ZIF design.
SPGA chips used staggered pins on the underside of the chip rather than in standard rows and columns. This was done to move pins closer together and decrease overall size of the chip when a large number of pins is required.
FC-PGA were used for most modern processors. There were problems with the installation of these packages. When you would go to intall your heatsink if you pressed down on one side of the heatsink excessively during the installation you would risk cracking the silcon die (the heatsink sat on-top of the die like a pedestal) and destroying the chip.
SECC or SEPP consisted of the CPU and optional separate L2 cache chips mounted on a circuit board that looked similar to an over-sized memory module and that plugged into a slot. In some cases, the boards were covered with a plastic cartridge cover. A cost-effective method for integrating the L2 cache into the processor.
SEP was a less expensive version of the SECC just without the fancy plastic cover.
TYPES OF SOCKETS
Super Socket 7
Socket 370 (PGA-370)
Socket A (Socket 462)